Large numbers of identical integrated circuits such as microprocessors, memory devices, and digital signal processing devices are generally fabricated on a silicon wafer. Due to defects that may occur during fabrication, each IC (die) on the wafer is typically tested or sorted by test equipment such as automatic test equipment (ATE) machines and probe cards. The test signals are provided to each die through input or input/output (I/O) bond pads on each die, and the test results are monitored on output or I/O bond pads. The good die that pass the wafer-level test are then singulated and packaged typically by electrically connecting the bond pads to the package by means of bond wires, solder balls, or other contact structures. To accommodate the bonding wires or solder balls, the bond pads are generally very large relative to the circuit elements of the integrated circuit. Typical bond pad sizes are on the order of 100 μm (microns)×100 μm (4 mils×4 mils). The bond pads are also typically aligned in regular patterns such as peripherally along the outside perimeter of the die, in a grid pattern, or in a column or row generally through the center of the die (lead-on-center).
The bond pads allow each die as a whole to be functionally tested for specified timing parameters (AC parameters), DC parameters, and overall operation. The bonding pads may also be used to load test patterns and monitor test result from on chip test circuits such as SCAN circuitry and Built-In Self-Test (BIST) circuitry. The on-chip test circuits enhance the overall testing of a die by enabling individual testing of internal circuits or nodes. However, this comes at the expense of increasing the size of the die to accommodate the added test circuitry and additional bond pads needed to support the on-chip test circuitry.
If a die already has all of its peripheral, grid, or lead-on-center bond pad locations dedicated to a device function, then adding additional bond pads in the predetermined bond pad alignment to support the on-chip testing circuitry can result in a substantial increase in the size of the die. Generally, larger die are more prone to defects and consequently more expensive to manufacture. Additionally, on-chip testing circuitry can result in a significant increase in test time as many clock cycles may be required to load test input data and subsequently output test results from a few available bond pads. On-chip testing circuitry also does not allow for direct external access to internal circuit nodes. Test input data and test results must pass through the SCAN circuitry or BIST circuitry before it can be monitored. This introduces additional circuits that can mask failures in the circuit intended to be tested, or can introduce new failures caused by SCAN or BIST circuitry.
Additionally, many designs are I/O limited since only a limited number of leads (e.g., bond wires) may be accommodated in a given packaging scheme. Moreover, to test I/O functionality of a chip, these same lead locations must be used. It would be advantageous to access more points in a circuit, especially for testing. It would also be advantageous if the access points could be located with a high degree of positional freedom. Small size, large number, and arbitrary or selected positioning of the access points would also be advantageous.